In a phase-locked loop (PLL), a phase frequency detector compares the phase and frequency of an output signal that is generated by a variable frequency oscillator to the phase and frequency of an input “reference” signal. Based on the comparison, the PLL adjusts the variable frequency oscillator to establish and maintain a constant phase relationship between the output signal and the input signal. Once the phase difference between the two signals becomes substantially constant in time, the PLL is said to be “in lock.”
Often, rather than comparing the phase and frequency of the output signal directly to the phase and frequency of the input signal, a frequency divider is used to first reduce the frequency of the output signal by a division factor to generate a comparison signal. The phase frequency detector then compares the phase and frequency of the comparison signal to the phase and frequency of the input signal and any adjustment needed to the variable frequency oscillator is made based on this comparison.
The amount of frequency variation between the input signal and the comparison signal over which the PLL can adjust the variable frequency oscillator such that the frequencies of the two signals are made equal and the PLL acquires lock is referred to as the pull-in range. A digital PLL (DPLL) (i.e., a PLL that includes component(s) that process and/or provide discrete-time signals) often suffers from a limited pull-in range due to the implementation of its phase frequency detector. Solutions to extend the pull-in range of the DPLL exist. However, these solutions often come at the cost of increased phase noise and/or spurs on the output signal produced by the DPLL.
The embodiments of the present disclosure will be described with reference to the accompanying drawings. The drawing in which an element first appears is typically indicated by the leftmost digit(s) in the corresponding reference number.